Processing a high-volume, concurrent, and stateful stream of sequential financial network transactions without introducing latency fluctuations or performance stalls caused by operating system kernel overhead, thread context-switching, lock contention, and dynamic heap memory fragmentation.
Nischal Khanal
Systems & Performance Engineer
Software Engineer exploring systems, market infrastructure, and performance engineering
Featured Projects
What I'm up to now?
View what I'm focused on right now →Recent Writing
Decoupled Vector-Map Data Layout for Allocation-Free Limit Order Book
Jun 24, 2026Takeaway:An architectural guide to a 3-layer C++ order book layout using a flat vector memory pool and shallow map to achieve O(1) FIFO queue operations.
Python GIL Trap in Low-Latency Async Pipelines
Jun 17, 2026Takeaway:We stopped market-volatility event loop freezes by micro-batching Pydantic payloads into a single GIL-efficient thread handoff for flatline reliability
Stabilizing a High-Frequency Trading Gateway: How We Reclaimed Our Event Loop Under Extreme Market Volatility
Jun 15, 2026Takeaway:Fixed trading pipeline message drops by replacing blocking writes and GIL-heavy validation with an async micro-batching architecture